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Creating Safe State Machines
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2. Hard-encoded 'Safe' State Machines
Regardless of how many states you have, if you use the "bit-level" encoding scheme, the optimized result will be "safe." This requires you to specify bit patterns for your states. For example, in VHDL use std_logic_vector to define your state type, then you can detect the undesired states using the "others" statement in the state decoding process or by explicitly defining if:
current_state = (undesired states) or current_state /= (desired states).

For the example shown in Figure 1, you can use the following statements to declare the state values:

SUBTYPE STATE_TYPE IS std_logic_vector(3 DOWNTO 0);

CONSTANT s0 : STATE_TYPE := "0001";
CONSTANT s1 : STATE_TYPE := "0010";
CONSTANT s2 : STATE_TYPE := "0100";
CONSTANT s3 : STATE_TYPE := "1000";

SIGNAL current_state : STATE_TYPE ;
SIGNAL next_state : STATE_TYPE ;

The example uses one-hot encoding; it also applies to any other encoding algorithm.

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